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1st International Workshop on NEURO-INSPIRED ACCELERATORS for COMPUTING (NIAC)
held in conjunction with HiPEAC '13 conference (http://www.hipeac.net/conference)
21-23 January 2013,
Due to increasingly stringent energy constraints, multi-cores are shifting towards heterogeneous multi-cores, combinations of cores and accelerators. As a result, one of the key micro-architecture issues is to determine what these accelerators should be.
Two major trends point to hardware neural networks as accelerators with great potential: increasing process variability resulting in multiple defects, and the increasing importance of high-performance applications tolerating approximate results (e.g., recognition and mining applications). Both trends match well the intrinsic robustness capabilities of neural networks. The purpose of this workshop is to stimulate the development and adoption of hardware neural network accelerators in the architecture community.
- Neuro-inspired architecture design
- Applications of neuro-inspired architectures
- Alternative technologies and devices (analog, 3D, memristors, …) for neuro-inspired architectures
- Programming and compilation techniques for neuro-inspired architectures
Paper Submission: November 1st, 2012
Author Notification: November 23, 2012
Camera-Ready Paper: December 7, 2012
Short to long contributions are welcome, varying from 4 to 10 pages.
The articles will be made available online, but no proceedings will be published, so that submission to the workshop is compatible with later submission to conferences and journals.
Rodolphe Heliot, CEA-LETI,
Olivier Temam, INRIA Saclay